HC4GX15 Datasheet, PDF (272/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–8
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2 provides a brief description of the ALTGX megafunction ports.
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 1 of 14)
Port Name
Input/Output
Description
Clock Multiplier Unit (CMU)
pll_inclk
pll_locked
pll_powerdown
coreclkout
Input
Output
Input
Output
Input reference clock for the CMU phase-locked
loop (PLL).
CMU PLL lock indicator. A high level indicates
that the CMU PLL is locked to the input
reference clock; a low level indicates that the
CMU PLL is not locked to the input reference
clock.
Asynchronous signal.
CMU PLL power down. When asserted high, the
CMU PLL is powered down. When de-asserted
low, the CMU PLL is active and locks to the
input reference clock.
Note: Asserting the pll_powerdown signal
does not power down the REFCLK buffers.
Asynchronous signal. The minimum
pulse-width is 1 μs (pending characterization).
Core fabric-transceiver interface clock.
Generated by the CMU0 clock divider in the
transceiver block in ×4 bonded channel
configurations. Generated by the CMU0 clock
divider in the master transceiver block in ×8
bonded channel configurations. Not available in
non-bonded channel configurations.
This clock is used to clock the write port of the
transmitter phase compensation FIFOs in all
bonded channels. Use this clock signal to clock
parallel data tx_datain from the core fabric
into the transmitter phase compensation FIFO
of all bonded channels.
This clock is used to clock the read port of the
receiver phase compensation FIFOs in all
bonded channels with rate match FIFO enabled.
Use this signal to clock parallel data
rx_dataout from the receiver phase
compensation FIFOs of all bonded channels
(with rate match FIFO enabled) into the core
fabric.
Scope
Transceiver
block
Transceiver
block
Transceiver
block
Transceiver
block
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation