HC4GX15 Datasheet, PDF (573/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
2–115
■ By doing so, the dynamic reconfiguration controller overwrites the
logical tx pll value stored in the .mif with the logical reference index of the
other CMU0 PLL.
■ The transceiver channel of another transceiver block is then reconfigured to
listen to the CMU0 PLL of its other transceiver block.
General Guidelines for Specifying the Input Reference Clocks
The following are general guidelines for setting up the input reference clocks in the
Reconfig Clks screen of the ALTGX MegaWizard Plug-In Manager.
■ Assign the identification numbers to all input reference clocks that are used in the
design in the Reconfig Clks screen. You can set up a maximum of 10 input
reference clocks and assign identification numbers from 1 to 10 (1, 2, 3, 4, 5, 6, 7, 8,
9, and 10).
■ Keep the identification numbers consistent for all the .mifs generated in the
design.
■ Maintain the input reference clock frequencies settings for all the .mifs.
Consider you have two ALTGX instances in your design. Table 2–31 describes how to
set up the identification numbers for the input reference clocks for all the .mifs
involved in the design.
Table 2–31. Example for the Specifying the Input Reference Clocks (Part 1 of 4)
ALTGX Instances and Settings
ALTGX Setting
What is the number of
channels? option in the
General screen
ALTGX Instance 1
1
(Regular transceiver channel)
ALTGX Instance 2
1
(Regular transceiver channel)
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3