HC4GX15 Datasheet, PDF (393/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–129
■ Optional byte serializer (enabled for 16-bit and disabled for 8-bit core
fabric-transceiver interface)
■ 8B/10B encoder
■ 10:1 serializer
■ Transmitter buffer with receiver detect circuitry
The receiver datapath in PCI Express (PIPE) mode consists of:
■ Receiver buffer with signal detect circuitry
■ 1:10 deserializer
■ Word aligner that implements PIPE-compliant synchronization state machine
■ Optional rate match FIFO (clock rate compensation) that can tolerate up to
600 PPM frequency difference
■ 8B/10B decoder
■ Optional byte deserializer (enabled for 16-bit and disabled for 8-bit core
fabric-transceiver interface)
■ Receiver phase compensation FIFO
■ PIPE interface
Table 1–32 shows features supported in PIPE functional mode for 2.5 Gbps and
5 Gbps data rate configurations.
Table 1–32. Supported Features in PCI Express (PIPE) Mode
Feature
×1, ×4, ×8 link configurations
PIPE-compliant synchronization state machine
±300 PPM (total 600 PPM) clock rate compensation
8-bit core fabric-transceiver interface
16-bit core fabric-transceiver interface
Transmitter buffer electrical idle
Receiver Detection
8B/10B encoder disparity control when transmitting compliance pattern
Power state management
Receiver status encoding
Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate
Dynamically selectable transmitter margining for differential output voltage control
Dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 dB
Dynamically selectable full-swing and half-swing transmitter output voltage levels
2.5 Gbps
(Gen1)
v
v
v
v
v
v
v
v
v
v
—
—
—
—
5 Gbps
(Gen2)
v
v
v
—
v
v
v
v
v
v
v
v
v
v
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3