HC4GX15 Datasheet, PDF (118/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–8
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Receiver
Figure 8–6. HardCopy IV Receiver Block Diagram
Input data stream
+
–
DPA Bypass Multiplexer
DQ
Data
Realignment
Circuitry
Eight Phase Clocks
data retimed_data
DPA
DPA_clk
Synchronizer
8
Dedicated
Receiver
Interface
rx_inclk
PLL _Lx /
PLL_Rx
diffioclk
load_en
10
Internal
Logic
Regional or
Global Clock
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that compensates for
any phase difference between the DPA clock and the data realignment block. If
necessary, the data realignment circuit inserts a single bit of latency in the serial bit
stream to align to the word boundary. The deserializer includes shift registers and
parallel load registers, and sends a maximum of 10 bits to the internal logic. The data
path in the HardCopy IV receiver is clocked by either a diffioclk signal or the DPA
recovered clock. The deserialization factor can be statically set to 4, 6, 7, 8, or 10 by
using the Quartus II software. The left or right PLLs (PLL_Lx/PLL_Rx) generate the
load enable signal, which is derived from the deserialization factor setting.
You can bypass the HardCopy IV deserializer in the Quartus II MegaWizard Plug-In
Manager to support DDR (×2) or SDR (×1) operations. The DPA and the data
realignment circuit cannot be used when the deserializer is bypassed. The IOE
contains two data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource, from the left or
right PLLs, or from the top or bottom PLLs. Figure 8–7 shows the deserializer bypass
data path.
Figure 8–7. Deserializer Bypass
rx_in
DPA
Circuitry
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Deserializer
HardCopy
Logic Array
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation