HC4GX15 Datasheet, PDF (452/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Loopback Modes
Loopback Modes
HardCopy IV GX devices provide various loopback options that allow you to verify
the working of different functional blocks in the transceiver channel. The available
loopback options are:
■ Serial loopback—available in all functional modes except PCI Express (PIPE)
mode
■ Reverse serial loopback—available in Basic mode only
■ Reverse serial pre-CDR loopback—available in Basic mode only
■ PIPE reverse parallel loopback—supported in PIPE protocol only
Serial Loopback
The serial loopback option is available for all functional modes except PCI Express
(PIPE) mode. Figure 1–156 shows the datapath for serial loopback. The data from the
core fabric passes through the transmitter channel and gets looped back to the
receiver channel, bypassing the receiver buffer. The received data is available to the
core logic for verification. Using this option, you can check the working for all
enabled PCS and PMA functional blocks in the transmitter and receiver channel.
When you enable the serial loopback option, the ALTGX MegaWizard Plug-In
Manager provides the rx_seriallpbken port to dynamically enable serial loopback
on a channel-by-channel basis. Set the rx_seriallpbken signal to logic high to
enable serial loopback.
When serial loopback is enabled, the transmitter channel sends the data to both the
tx_dataout output port and to the receiver channel. The differential output voltage
on the tx_dataout ports is based on the selected V_OD settings. The looped back data
is received by the receiver CDR and is retimed through different clock domains. You
must provide an alignment pattern for the word aligner to enable the receiver channel
to retrieve the byte boundary.
Figure 1–156. Serial Loopback Datapath
TX
Phase
Compen-
sation
FIFO
Byte
Serializer
BIST PRBS, High-Freq,
Low-Freg pattern
generator
8B/10B
Encoder
Transmitter Channel PCS ^{Transmitter Channel PMA}
Serializer
Core
Fabric
Receiver Channel PCS
BIST PRBS verifier
Serial loop back
can be dynamically enabled
Receiver Channel
PMA
RX
Phase
Compen-
sation
FIFO
Byte
Ordering
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
De-
serializer
Receiver
CDR
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation