HC4GX15 Datasheet, PDF (101/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 7: External Memory Interfaces in HardCopy IV Devices
7–35
HardCopy IV External Memory Interface Features
The DQS postamble circuitry, shown in Figure 7–21, ensures that data is not lost when
there is noise on the DQS line at the end of a read postamble time. HardCopy IV
devices have a dedicated postamble register that can be controlled to ground the
shifted DQS signal used to clock the DQ input registers at the end of a read operation.
This ensures that any glitches on the DQS input signals at the end of the read
postamble time do not affect the DQ IOE registers.
Figure 7–21. HardCopy IV DQS Postamble Circuitry
DQS Enable
B
A
reset
gated_dqs control
DFF
PRN
QD
V_CC
DQS'
CLR
Postamble
Enable
Resynchronization
Clock
Postamble
Clock
DQ
DQS Bus
DQ
dqsenable
DQ
In addition to the dedicated postamble register, HardCopy IV devices also have an
HDR block inside the postamble enable circuitry. These registers are used if the
controller is running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block in Figure 7–21 is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–27). The AND gate after the postamble register outputs is used to avoid
postamble glitches from a previous read burst on a non-consecutive read burst. This
scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency
for dqsenable deassertion, as shown in Figure 7–22.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1