HC4GX15 Datasheet, PDF (288/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
CMU Channels
CMU0 Channel
The CMU0 channel, shown in Figure 1–8, contains the following blocks:
■ CMU0 PLL
■ CMU0 clock divider
Figure 1–8. Block Diagram of the CMU0 Channel
pll_locked
pll_powerdown
PLL Cascade Clock
Global Clock Line
Dedicated refclk0
Dedicated refclk1
ITB Clock Lines
6
CMU0 Channel
CMU0 PLL
input
reference clock
CMU0 PLL
CMU0 PLL
High-Speed
Clock (1)
CMU1 PLL
High-Speed Clock
High-Speed Serial Clock
for Bonded Modes (2)
CMU0 Clock ^{Low-Speed Parallel Clock}
Divider
for Bonded Modes
PCIE_gen2switch
(to PCI Express rateswitch controller block in the CCU)
PCIE_gen2switch_done
(to PCI Express rateswitch controller block in the CCU)
Notes to Figure 1–8:
(1) In non-bonded functional modes (for example, GIGE functional mode), the transmitter channel uses the transmitter local clock divider to divide
this high-speed clock output to provide clocks for its PMA and PCS blocks.
(2) Used in XAUI, Basic ×4, and PCI Express (PIPE) ×4 functional modes. In PIPE ×8 functional mode, only the CMU0 channel of the master transceiver
block provides clock output to all eight transceiver channels configured in PIPE functional mode.
CMU0 PLL
Figure 1–9 shows a block diagram of the CMU0 PLL.
Figure 1–9. Block Diagram of the CMU0 PLL
CMU0 PLL
PLL Cascade Clock
Global Clock Line
Dedicated refclk0
Dedicated refclk1
ITB Clock Lines (1)
6
CMU0 PLL
Input Reference
Clock
/1, /2, /4, /8
PFD
/M
Charge Pump
+ Loop Filter
V_CO
CMU0
High-Speed
Clock
/L
Note to Figure 1–9:
(1) The inter transceiver block (ITB) clock lines shown are the maximum value. The actual number of ITB lines in your device depends on the number
of transceiver blocks on one side of the device.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation