HC4GX15 Datasheet, PDF (18/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–8
Chapter 1: HardCopy IV Device Family Overview
Features
Table 1–5 and Table 1–6 show the available packages for HardCopy IV devices.
Table 1–5. HardCopy IV GX and Stratix IV GX Package, I/O Pin Count, LVDS Pair Count, and Transceiver Mapping
(Note 1), (2)
HardCopy IV GX
ASIC
HC4GX15
HC4GX25
HC4GX35
LAF780 (3)
372, 28, 8+0
—
—
LF780 (4)
257, 0, 8+0
289, 0, 16+0
—
LF1152 (5)
—
564, 44, 16+0
—
—
564, 44, 16+8
—
FF1152 (5)
—
—
564, 44, 16+8
—
564, 44, 16+8
564, 44, 16+8
FF1517 (6)
—
—
744, 88, 24+12
Companion
Mapping
Stratix IV GX
FPGA Prototype
F780
H780
F1152
F1152
F1152
H1152
F1517
EP4SGX70 _{372, 28, 8+0}
—
—
—
—
—
—
EP4SGX110 _{372, 28, 8+0}
—
372, 28, 16+0
—
—
—
—
EP4SGX180 _{372, 28, 8+0}
—
564, 44, 16+0 564, 44, 16+8
—
—
744, 88, 24+12
EP4SGX230 _{372, 28, 8+0}
—
564, 44, 16+0 564, 44, 16+8 564, 44, 16+8
—
744, 88, 24+12
EP4SGX290
—
289, 0, 16+0 564, 44, 16+0 564, 44, 16+8
—
—
744, 88, 24+12
EP4SGX360
—
289, 0, 16+0 564, 44, 16+0 564, 44, 16+8 564, 44, 16+8
—
744, 88, 24+12
EP4SGX530
—
—
—
—
—
564, 44, 16+8 744, 88, 24+12
Notes to Table 1–5:
(1) The numbers in the table indicate I/O pin count, full duplex LVDS pairs, and transceivers (PMA and PCS) + CMU transceivers (PMA Only).
(2) The first letter (two letters in the LA package) in the HardCopy IV GX package name refers to the following: F–Performance-optimized flip chip
package, L or LA –Cost-optimized flip chip package.
(3) The I/O pin count for the LAF780 package includes the four dedicated clock inputs (CLK1n, CLK1p, CLK3n, and CLK3p).
(4) The I/O pin count for the LF780 package includes one dedicated clock input (CLK1p).
(5) The I/O pin count for the F1152 package includes the four dedicated clock inputs (CLK1n, CLK1p, CLK10n, and CLK10p).
(6) The I/O pin count for the F1517 package includes the eight dedicated clock inputs (CLK1n, CLK1p, CLK3n, CLK3p, CLK8n, CLK8p, CLK10n,
and CLK10p).
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation