HC4GX15 Datasheet, PDF (660/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–30
Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
Switching Characteristics
Table 1–34. Sampling Window (SW) - Read Side—Preliminary (Note 1) (Part 2 of 2)
Location (2)
Memory Type
Sampling Window (ps)
Setup
Hold
DDR3 (>400MHz) (3)
282
56
DDR3
344
85
DDR2
HIO
DDR1
213
162
236
178
QDRII/II+
218
203
RLDRAM II (>333MHz) (4)
198
183
Note to Table 1–34:
(1) Pending silicon Characterization.
(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os
in the left and right banks.
(3) Pending IP support. Actual achievable performance is based on design and system-specific
factors. For DDR3 > 400MHz support, contact Altera.
(4) Pending IP support. Actual achievable performance is based on design and system-specific
factors. For RLDRAM II > 333MHz support, contact Altera.
Table 1–35. Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note 1)
Location (2)
Memory Type
TCCS (ps)
Lead
Lag
DDR3 (>400MHz) (3)
234
286
DDR3
344
347
DDR2
VIO
DDR1
270
380
275
396
QDRII/II+
294
408
RLDRAM II (>333MHz) (4)
346
356
DDR3 (>400MHz) (3)
282
56
DDR3
344
347
DDR2
HIO
DDR1
270
380
275
396
QDRII/II+
294
408
RLDRAM II (>333MHz) (4)
346
356
Notes to Table 1–35:
(1) Pending silicon characterization.
(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right
banks.
(3) Pending IP support. Actual achievable performance is based on design and system-specific factors. For DDR3 >
400 MHz support, contact Altera.
(4) Pending IP support. Actual achievable performance is based on design and system-specific factors. For
RLDRAM II > 333 MHz support, contact Altera.
DLL and DQS Logic Block Specifications
Table 1–36 describes the delay-locked loop (DLL) frequency range specifications for
HardCopy IV devices.
HardCopy IV Device Handbook Volume 4
© June 2009 Altera Corporation