HC4GX15 Datasheet, PDF (280/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–16
Chapter 1: HardCopy IV GX Transceiver Architecture
Transceiver Port List
Table 1–2. HardCopy IV GX ALTGX Megafunction Ports (Part 9 of 14)
Port Name
rx_signaldetect
rx_seriallpbken
Input/Output
Description
Output
Signal threshold detect indicator. This feature is
available only in PCI Express (PIPE) mode. A
high level indicates that the signal present at the
receiver input buffer is above the programmed
signal detection threshold value.
If the electrical idle inference block is disabled
in PIPE mode, the rx_signaldetect
signal is inverted and driven on the
pipeelecidle port.
Asynchronous signal.
Input
Serial loopback control port.
0–normal datapath, no serial loopback
1–serial loopback
Transmitter Physical Coding Sublayer Ports
Transmitter Phase Compensation FIFO
tx_datain
Input
tx_clkout
Output
tx_coreclk
Input
tx_phase_comp_fifo_error
Output
Parallel data input from the core fabric to the
transmitter. The bus width depends on the
channel width multiplied by the number of
channels per instance.
Core fabric-transceiver interface clock. Each
channel has a tx_clkout signal in
non-bonded channel configurations. Use this
clock signal to clock the parallel data
tx_datain from the core fabric into the
transmitter. This signal is not available in
bonded channel configurations.
Optional write clock port for the transmitter
phase compensation FIFO. If not selected, the
Quartus II software automatically selects
tx_clkout/coreclkout as the write
clock for transmitter phase compensation FIFO.
If selected, you must drive this port with a clock
that is frequency locked to
tx_clkout/coreclkout.
Transmitter phase compensation FIFO full or
empty indicator. A high level indicates that the
transmitter phase compensation FIFO is either
full or empty.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation