HC4GX15 Datasheet, PDF (46/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 5: Clock Networks and PLLs in HardCopy IV Devices
5–6
PLLs in HardCopy IV Devices
Table 5–4. HardCopy IV PLL Features (Part 2 of 2)
Feature
HardCopy IV Top/Bottom PLLs
HardCopy IV Left/Right PLLs
Input clock switchover
Yes
Yes
Notes to Table 5–4:
(1) Provided input clock jitter is within input jitter tolerance specifications.
(2) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(3) The smallest phase shift is determined by the voltage-control oscillator (VCO) period divided by eight. For degree increments, the HardCopy IV
device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and
divide parameters.
Figure 5–1 shows the PLL locations in HardCopy IV devices. Some PLLs are not
available depending on the density and package of the HardCopy IV device.
Figure 5–1. HardCopy IV PLL Locations
PLL_L1_CLK L1
Top/Bottom PLLs
Top/Bottom PLLs
CLK[12..15]
T1 T2
R1 PLL_R1_CLK
Left/Right PLLs
Left/Right PLLs
L2
CLK[0..3]
L3
Q1 Q2
Q4 Q3
R2
CLK[8..11]
R3
Left/Right PLLs
Left/Right PLLs
PLL_L4_CLK ^L4
Top/Bottom PLLs
B1 B2
CLK[4..7]
Top/Bottom PLLs
R4 PLL-R4_CLK
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1