HC4GX15 Datasheet, PDF (67/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7. External Memory Interfaces in
HardCopy IV Devices
HIV51007-2.1
This chapter describes the hardware features that support high-speed memory
interfacing for each double data rate (DDR) memory standard in HardCopy^® IV
devices. HardCopy IV devices feature delay-locked loops (DLLs), phase-locked loops
(PLLs), dynamic on-chip termination (OCT), read and write leveling, and deskew
circuitry.
This chapter contains the following sections:
■ “Memory Interfaces Pin Support” on page 7–6
■ “HardCopy IV External Memory Interface Features” on page 7–23
Similar to the Stratix^® IV I/O structure, the HardCopy IV I/O structure has been
redesigned to provide flexible and high-performance support for existing and
emerging external memory standards. These include high-performance DDR memory
standards such as DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM, and
RLDRAM II.
HardCopy IV devices offer the same external memory interface features found in
Stratix IV devices. These features include DLLs, PLLs, dynamic OCT, trace mismatch
compensation, read and write leveling, deskew circuitry, half data rate (HDR) blocks,
4- to 36-bit DQ group widths, and DDR external memory support on all sides of the
HardCopy IV device. HardCopy IV devices provide an efficient architecture to
quickly and easily fit wide external memory interfaces with the small modular I/O
bank structure.
1 HardCopy IV devices are designed to support the same I/O standards and
implementation guidelines for external memory interfaces as Stratix IV devices.
In addition, a self-calibrating megafunction (ALTMEMPHY), optimized to take
advantage of the HardCopy IV I/O structure, and the Quartus^® II timing analysis tool
(TimeQuest Timing Analyzer) provide a complete solution for the highest reliable
frequency of operation across process, voltage, and temperature (PVT) variations.
f For more information about the ALTMEMPHY megafunction, refer to the External
DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY).
Altera recommends enabling the PLL reconfiguration feature and the DLL phase
offset feature (DLL reconfiguration) for HardCopy IV devices. Because HardCopy IV
devices are mask programmed, they cannot be changed after the silicon is fabricated.
By implementing these two features, you can perform timing adjustments to improve
or resolve timing issues after the silicon is fabricated.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1