HC4GX15 Datasheet, PDF (106/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–40
Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Figure 7–28. HardCopy IV IOE Output and Output-Enable Path Registers (Note 1)
From Core (2)
Half Data Rate to Single Data Rate Output-Enable Registers
DQ
DFF
0
1
From Core (2)
D
Q
DQ
DFF
DFF
From Core (wdata0) (2)
From Core (wdata1) (2)
From Core (wdata2) (2)
From Core (wdata3) (2)
Half-Rate Clock (3)
Half Data Rate to Single Data Rate Output Registers
DQ
DFF
DQ
DFF
0
1
DQ
DFF
DQ
DFF
DQ
DFF
0
1
D
Q
DFF
Alignment
Clock (3)
DQ
DFF
Alignment Registers (4)
D
Q
DFF
Alignment Registers (4)
DQ
DFF
DQ
DFF
DQ
DFF
DQ
DFF
Double Data Rate Output-Enable Registers
DFF
DQ
OE Reg A_OE
1
0
DFF
DQ
OR2
OE Reg BOE
Double Data Rate Output Registers
DFF
DQ
1
Output Reg Ao
0
DFF
DQ
TRI
DQ or DQS
Output Reg Bo
Write
Clock (5)
Notes to Figure 7–28:
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the ASIC core are at half the frequency of the memory interface.
(3) Half-rate and alignment clocks come from the PLL.
(4) These registers are only used in DDR3 SDRAM interfaces.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset
between them.
The output path is designed to route combinational or registered SDR outputs and
full-rate or half-rate DDR outputs from the core. Half-rate data is converted to
full-rate data using the HDR block, clocked by the half-rate clock from the PLL. The
resynchronization registers are also clocked by the same 0° system clock, except in the
DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling registers are
clocked by the write-leveling clock.
For more information about the write leveling delay chain, refer to “Leveling
Circuitry” on page 7–36.
The output-enable path has a structure similar to the output path. You can have a
combinational or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. You also have the resynchronization registers
similar to the output path registers structure, ensuring that the output enable path
goes through the same delay and latency as the output path.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation