HC4GX15 Datasheet, PDF (588/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–130
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller
Figure 2–57 shows this scenario before and after dynamic reconfiguration.
Figure 2–57. Before and After Example of CMU PLL Reconfiguration
refclk0 100 MHz
refclk1 125 MHz
clock
mux
CMU Channels
2 Gbps
CMU0 PLL
clock
mux
2.5 Gbps
CMU1 PLL
TX only CHANNEL 1
Logical
TX PLL
select
Local
Divider
6.25 Gbps
digital+analog logic
TX only CHANNEL 2
Logical
TX PLL
select
Local
Divider
6.25 Gbps
digital+analog logic
TX only CHANNEL 3
Logical
TX PLL
select
Local
Divider
6.25 Gbps
digital+analog logic
TX only CHANNEL 4
Logical
TX PLL
select
Local
Divider
6.25 Gbps
digital+analog logic
Blocks reconfigured using CMU PLL Reconfiguration mode
You can achieve this by reconfiguring the CMU0 PLL once to run for 2 Gbps. This, in
turn, changes the transmit data rate of all four channels listening to this CMU0 PLL.
You must enable .mif generation. Change the settings shown in Table 2–36 and save
them in the .mif.
Table 2–36. CMU PLL Reconfiguration Scenario (Part 1 of 2)
ALTGX Instances
ALTGX_RECONFIG Instance
ALTGX Setting
What is the effective data
rate? option
Four TX Only
Instances
2 Gbps
ALTGX_RECONFIG
Setting
Channel and TX PLL
select/reconfig option
ALTGX_RECONFIG
Instance
Enabled
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation