HC4GX15 Datasheet, PDF (413/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–149
1 The link being active is interpreted as the physical layer device coming out of
electrical idle in the L0 state of the LTSSM state machine.
Figure 1–119 shows the PCI Express (PIPE) cold reset timing requirements.
Figure 1–119. PCI Express (PIPE) Cold Reset Requirements
1
2
3
4
Power Rail
PERST#
TPVPERL 100 ms
T2-3
d"20 ms
T2-4
d"100 ms
Marker 1: Power becomes stable
Marker 2: PERST# gets de-asserted
Marker 3: Maximum time for Marker 2 for
the LTSSM to enter the Detect state
Marker 4: Maximum time for Marker 2 for
the link to become active
XAUI Mode
The time taken by a PCI Express (PIPE) port implemented using the HardCopy IV GX
device to go from power up to link active state is described below:
■ Power-on reset—begins after power rails become stable. Typically takes 12 ms
■ Time taken from de-assertion of PERST# to link active—typically takes 40 ms
(pending characterization and verification of PIPE soft IP and hard IP)
XAUI is an optional, self-managed interface that you can insert between the
reconciliation sublayer and the PHY layer to transparently extend the physical reach
of the XGMII.
XAUI addresses several physical limitations of the XGMII. XGMII signaling is based
on the HSTL Class 1 single-ended I/O standard, which has an electrical distance
limitation of approximately 7 cm. Because XAUI uses a low-voltage differential
signaling method, the electrical limitation is increased to approximately 50 cm.
Another advantage of XAUI is simplification of backplane and board trace routing.
XGMII is composed of 32 transmit channels, 32 receive channels, 1 transmit clock,
1 receive clock, 4 transmitter control characters, and 4 receive control characters for a
74-pin wide interface. XAUI, on the other hand, only consists of 4 differential
transmitter channels and 4 differential receiver channels for a 16-pin wide interface.
This reduction in pin count significantly simplifies the routing process in the layout
design.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3