HC4GX15 Datasheet, PDF (399/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–135
Table 1–34. Logic Levels for the PHY-MAC Layer
Power State
tx_detectrxloopback
P0
0: normal mode
1: datapath in loopback mode
P0s
Don’t care
P1
0: Electrical Idle
1: receiver detect
P2
Don’t care
tx_forceelecidle
0: Must be de-asserted
1: Illegal mode
0: Illegal mode
1: Must be asserted in this state
0: Illegal mode
1: Must be asserted in this state
De-asserted in this state for sending
beacon. Otherwise asserted.
Receiver Status
The PCI Express (PIPE) specification requires the PHY to encode the receiver status on
a 3-bit RxStatus[2:0] signal. This status signal is used by the PHY-MAC layer for
its operation.
The PIPE interface block receives status signals from the transceiver channel PCS and
PMA blocks and encodes the status on the 3-bit output signal pipestatus[2:0] to
the core fabric. The encoding of the status signals on pipestatus[2:0] is compliant
with the PIPE specification and is listed in Table 1–35.
Table 1–35. Encoding of the Status Signals on pipestatus[2:0]
pipestatus[2:0]
Description
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
Received data OK
One SKP symbol added
One SKP symbol deleted
Receiver detected
8B/10B decode error
Elastic buffer (rate match FIFO) overflow
Elastic buffer (rate match FIFO) underflow
Received disparity error
Error Condition Priority
—
5
6
—
1
2
3
4
Two or more of the error conditions (for example, 8B/10B decode error [code group
violation], rate match FIFO overflow or underflow, and receiver disparity error), can
occur simultaneously. The PIPE interface follows the priority listed in Table 1–35
while encoding the receiver status on the pipestatus[2:0] port. For example, if
the PIPE interface receives an 8B/10B decode error and disparity error for the same
symbol, it drives 3'b100 on the pipestatus[2:0] signal.
Fast Recovery Mode
The PIPE Base specification fast training sequences (FTS) are used for bit and byte
synchronization to transition from L0s to L0 (PIPE P0s to P0) power states. When
transitioning from L0s to L0 power state, the PIPE Base Specification requires the
physical layer device to acquire bit and byte synchronization after receiving a
maximum of 255 FTS (~4 us at Gen1 data rate and ~2 us at Gen2 data rate).
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3