HC4GX15 Datasheet, PDF (362/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
In XAUI mode, the rate match FIFO does not automatically insert or delete code
groups to overcome FIFO empty and full conditions, respectively. It asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock
cycles to indicate rate match FIFO full and empty conditions, respectively.
1 In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Rate Match FIFO in GIGE Mode
In GIGE mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The GIGE protocol requires the transmitter to send idle ordered sets
/I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering
to rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate match FIFO is capable of deleting or inserting the /I2/
(/K28.5/D16.2/) ordered set to prevent the rate match FIFO from overflowing or
under-running during normal packet transmission. The rate match FIFO is also
capable of deleting or inserting the first two bytes of the /C2/ ordered set
(/K28.5/D2.2/Dx.y/Dx.y/) to prevent the rate match FIFO from overflowing or
under-running during the auto negotiation phase.
The rate match FIFO can insert or delete as many /I2/ or /C2/ (first two bytes) as
necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate
rate match FIFO deletion and insertion events, respectively, are forwarded to the core
fabric. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are
asserted for two clock cycles for each deleted and inserted /I2/ ordered set,
respectively.
Figure 1–77 shows an example of rate match FIFO deletion in the case where three
symbols are required to be deleted. Because the rate match FIFO can only delete /I2/
ordered set, it deletes two /I2/ ordered sets (four symbols deleted).
Figure 1–77. Rate Match Deletion in GIGE Mode
/I2/ Ordered Set Deleted
datain
First /I2/ Ordered Set
Second /I2/ Ordered Set
Third /I2/ Ordered Set
Dx.y
K28.5
D16.2
K28.5
D16.2
K28.5
D16.2
Dx.y
dataout
Dx.y
K28.5
D16.2
Dx.y
rx_rmfifodatadeleted
Figure 1–78 shows an example of rate match FIFO insertion in the case where one
symbol is required to be inserted. Because the rate match FIFO can only delete /I2/
ordered set, it inserts one /I2/ ordered sets (two symbols inserted).
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation