HC4GX15 Datasheet, PDF (316/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–52
Chapter 1: HardCopy IV GX Transceiver Architecture
Transmitter Channel Datapath
Figure 1–39. Serializer Block in 8-Bit PCS-PMA Interface
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
parallel clock from local divider block
parallel clock from CMU0 clock divider
parallel clock from master transceiver block (1)
D1
D0
Low-Speed
Parallel Clock
D1
To Output Buffer
D0
serial clock from local divider block
serial clock from CMU0 clock divider
serial clock from master transceiver block (1)
High-Speed Serial Clock
Note to Figure 1–39:
(1) The CMU0 clock divider of the master transceiver block provides the clocks. It is used only in bonded modes (for example, Basic ×8, PCI Express
[PIPE] ×8 mode).
Figure 1–40. Serializer Bit Order (Note 1)
Low-speed parallel clock
High-speed serial clock
tx_datain[7..0]
01101010
00000000
tx_dataout[0]
0 1 0 1 0 11 0
Note to Figure 1–40:
(1) It is assumed that the input data to the serializer is 8 bits (channel width = 8 bits or 16 bits with the 8B/10B encoder disabled).
Transmitter Output Buffer
The HardCopy IV GX transmitter buffers support 1.4-V and 1.5-V pseudo current
mode logic (PCML) and can drive 40 inches of FR4 trace across two connectors. You
can set the transmitter buffer voltage levels (V_CCH) through the ALTGX MegaWizard
Plug-In Manager. With the 1.4 V and 1.5 V settings, you can run the transmitter
channel from 600 Mbps to 6.5 Gbps and 600 Mbps to 4.25 Gbps, respectively. The
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation