HC4GX15 Datasheet, PDF (367/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
1–103
Figure 1–84. Rate Match Insertion in Basic Double-Width Mode
First Skip Cluster
Second Skip Cluster
dataout[19:0]
Dx.y
dataout[9:0]
Dx.y
datain[19:10]
Dx.y
datain[9:0]
Dx.y
K28.0
K28.5
K28.0
K28.5
Dx.y
Dx.y
K28.0
K28.0
K28.5
Dx.y
K28.0
K28.0
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
K28.5
Dx.y
rx_rmfifodatainserted
K28.0
K28.0
K28.0
K28.0
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the core fabric
to indicate rate match FIFO full and empty conditions.
The rate match FIFO in Basic double-width mode automatically deletes the pair of
data byte that causes the FIFO to go full and asserts the rx_rmfifofull flag
synchronous to the subsequent pair of data bytes.
Figure 1–85 shows the rate match FIFO full condition in Basic double-width mode.
The rate match FIFO becomes full after receiving the 20-bit word D5D6.
Figure 1–85. Rate Match FIFO Full Condition in Basic Double-Width Mode
datain[19:10]
D2
D4
D6
D8
D10
D12
datain[9:0]
D1
D3
D5
D7
D9
D11
dataout[19:0]
D2
D4
D6
D10
D12
xx
dataout[9:0]
D1
D3
D5
D9
D11
xx
rx_rmfifofull
The rate match FIFO automatically inserts a pair of /K30.7/ ({9'h1FE,9'h1FE}) after the
data byte that causes the FIFO to go empty and asserts the rx_fifoempty flag
synchronous to the inserted pair of /K30.7/ ({9'h1FE,9'h1FE}).
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3