HC4GX15 Datasheet, PDF (589/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Design Examples: Dynamic Reconfiguration Controller (ALTGX_RECONFIG)
2–131
Table 2–36. CMU PLL Reconfiguration Scenario (Part 2 of 2)
ALTGX Instances
ALTGX_RECONFIG Instance
ALTGX Setting
Enable Channel and
Transmitter PLL
Reconfiguration option
Enable Channel and
Transmitter PLL
Reconfiguration option
What is the main transmitter
PLL reference index? option
How many input clocks?
option
What is the selected input
clock source for the
Transmitter PLL and Receiver
PLL? option
What is clock 0 input
frequency? option
Four TX Only
Instances
Enabled
ALTGX_RECONFIG
Setting
Enabled
1
Use
‘reconfig_address_en’
2
option
1
125 MHz
ALTGX_RECONFIG
Instance
Enabled
After generating the .mif, follow the steps listed in “CMU PLL Reconfiguration
Operation” on page 2–108 to write all the words.
Example 6: Dynamically Reconfiguring a Transceiver Channel between a GIGE
Configuration and a SONET/SDH OC48 Configuration
The ALTGX MegaWizard Plug-In Manager settings—for example, data path,
clocking, and core fabric-Transceiver interface width—are different for the GIGE
configuration versus the SONET/SDH OC48 configuration. The differences between
the two configurations are listed in Table 2–36.
Table 2–37. Differences between GIGE and SONET/SDH OC48 (Part 1 of 2)
Number
1
2
3
4
5
6
Functional Block
Core fabric-Transceiver
interface width
8B/10B enabled
Rate matcher enabled
Byte ordering block enabled
Clock used for synchronizing
the receive output data
(tx_dataout)
Data rate
GIGE
8
Yes
Yes
No
tx_clkout
(because rate matcher is
used)
1.25 Gbps
SONET/SDH OC48
16
No
No
Yes
rx_clkout
2.488 Gbps
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3