HC4GX15 Datasheet, PDF (246/668 Pages) Altera Corporation – HardCopy IV Device Handbook

4–12
Chapter 4: Matching Stratix IV Power and Configuration Requirements with HardCopy IV Devices
Examples of Mapping a Stratix FPGA Configuration to a HardCopy ASIC
Figure 4–10. Configuring FPGAs in a JTAG Chain Using a Microprocessor
V_CCPGM
V_CCPGM V_CCPGM
V_CCPGM V_CCPGM
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Stratix IV Device
Stratix IV Device
Stratix IV Device
V_CCPGM
10 kΩ
Memory
ADDR
DATA
Microprocessor
nSTATUS
(2) _DATA0
(2) _DCLK
(2) _nCONFIG
(2)
(2)
MSEL2 _{CONF_DONE}
MSEL1
(2) MSEL0
(3)
nCE
TDI
TDO
TMS TCK
nSTATUS
(2) _DATA0
(2) _DCLK
(2) _nCONFIG
(2)
(2)
MSEL2 _{CONF_DONE}
MSEL1
(2) MSEL0
(3)
nCE
TDI
TDO
TMS TCK
nSTATUS
(2) _DATA0
(2) _DCLK
(2) _nCONFIG
(2)
MSEL2 _{CONF_DONE}
(2) MSEL1
(2) MSEL0
(3)
nCE
TDI
TDO
TMS TCK
Notes to Figure 4–10:
(1) You can place the Stratix IV, Stratix III, Stratix II, Stratix, Cyclone^® III, Cyclone II, and Cyclone devices within the same JTAG chain for device
programming and configuration.
(2) Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If you only use JTAG configuration,
connect nCONFIG to V_CCPGM, and MSEL0, MSEL1, and MSEL2 to GND. Pull DATA0 and DCLK to either high or low.
(3) nCE must be connected to GND or driven low for successful JTAG configuration.
Figure 4–11 shows an example where the first Stratix IV device in the JTAG chain is
replaced by a HardCopy IV device.
Figure 4–11. Replacement of the First FPGA in the JTAG Chain with a HardCopy IV Device (Note 1)
V_{CC PGM}
V_CCPGM V_CCPGM
V_CCPGM V_CCPGM
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
HardCopy IV Device
Stratix IV Device
Stratix IV Device
V_CCPGM
10 kΩ
Memory
ADDR
DATA
Microprocessor
nSTATUS
NC _DATA0
NC _DCLK
(2) _nCONFIG
NC
NC
MSEL2 _{CONF_DONE}
MSEL1
NC MSEL0
(3)
nCE
TDI
TDO
TMS TCK
nSTATUS
(2) _DATA0
(2) _DCLK
(2) _nCONFIG
(2)
(2)
MSEL2 _{CONF_DONE}
MSEL1
(2) MSEL0
(3)
nCE
TDI
TDO
TMS TCK
nSTATUS
(2) _DATA0
(2) _DCLK
(2) _nCONFIG
(2)
MSEL2 _{CONF_DONE}
(2) MSEL1
(2) MSEL0
(3)
nCE
TDI
TDO
TMS TCK
Notes to Figure 4–11:
(1) You can place the Stratix IV, Stratix III, Stratix II, Stratix, Cyclone III, Cyclone II, and Cyclone devices within the same JTAG chain for device
programming configuration.
(2) Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If you use only JTAG configuration,
connect nCONFIG to V_CCPGM, and MSEL0, MSEL1, and MSEL2 to GND. Pull DATA0 and DCLK to either high or low.
(3) nCE must be connected to GND or driven low for successful JTAG configuration.
HardCopy IV Device Handbook, Volume 2
© June 2009 Altera Corporation