HC4GX15 Datasheet, PDF (455/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Loopback Modes
Figure 1–159. Reverse Serial Pre-CDR Loopback Datapath
Transmitter Channel PCS
1–191
Transmitter Channel PMA
Core
Fabric
RX Phase
Compen-
sation
FIFO
Byte
Ordering
Serializer
Receiver Channel PCS
Receiver Channel PMA
Reverse
Serial
Pre-CDR
Loopback
Byte
De-
Serializer
8B/10B
Decoder
Word
Aligner
De-
Serializer
Receiver
CDR
PCI Express (PIPE) Reverse Parallel Loopback
PCI Express (PIPE) reverse parallel loopback is only available in PIPE functional
mode for Gen1 and Gen2 data rates. As shown in Figure 1–160, the received serial
data passes through the receiver CDR, deserializer, word aligner, and rate matching
FIFO buffer. It is then looped back to the transmitter serializer and transmitted out
through the tx_dataout port. The received data is also available to the core fabric
through the rx_dataout port. This loopback mode is compliant with the PCI
Express (PIPE) specification 2.0. To enable this loopback mode, assert the
tx_detectrxloopback port.
1 This is the only loopback option supported in PCI Express (PIPE) functional mode.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3