HC4GX15 Datasheet, PDF (371/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
8B/10B Decoder in Double-Width Mode
Figure 1–90 shows the 8B/10B decoder in double-width mode.
Figure 1–90. 8B/10B Decoder in Double-Width Mode
datain[19:10]
8B/10B Decoder
(LSByte)
rx_dataout[15:8]
rx_ctrldetect[1]
rx_errdetect[1]
rx_disperr[1]
1–107
recovered clock or
tx_clkout[0]
datain[9:0]
Current Running Disparity
8B/10B Decoder
(LSByte)
rx_dataout[7:0]
rx_ctrldetect
rx_errdetect
rx_disperr
recovered clock or
tx_clkout[0]
In double-width mode, two 8B/10B decoders are cascaded for decoding the 20-bit
encoded data, as shown in Figure 1–91. The 10-bit LSByte of the received 20-bit
encoded data is decoded first and the ending running disparity is forwarded to the
8B/10B decoder responsible for decoding the 10-bit MSByte. The cascaded 8B/10B
decoder decodes the 20-bit encoded data into 16-bit data + 2-bit control identifier. The
MSB and LSB of the 2-bit control identifier corresponds to the MSByte and LSByte of
the 16-bit decoded data code group. The decoded data is fed to the byte deserializer or
the receiver phase compensation FIFO (if byte deserializer is disabled).
1 Each of the two cascaded 8B/10B decoders is compliant to Clause 36 in the IEEE802.3
specification.
The 8B/10B decoder operates in double-width mode only in Basic double-width
functional mode. You can enable or disable the 8B/10B decoder depending on your
proprietary protocol implementation.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3