HC4GX15 Datasheet, PDF (358/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
The rate match FIFO consists of a 20-word deep FIFO and necessary logic that controls
insertion and deletion of a skip character or ordered set, depending on the PPM
difference.
The rate match FIFO is mandatory and cannot be bypassed in the following functional
modes:
■ PCI Express (PIPE)
■ XAUI
■ GIGE
The rate match FIFO is optional in the following functional modes:
■ Basic single-width
■ Basic double-width
The rate match FIFO receives data from the word aligner (non-XAUI functional
modes) or deskew FIFO (XAUI functional mode) in the receiver datapath. It provides
the following status signals forwarded to the core fabric:
■ rx_rmfifodatainserted—indicates insertion of a skip character or ordered set
■ rx_rmfifodatadeleted—indicates deletion of a skip character or ordered set
■ rx_rmfifofull—indicates rate match FIFO full condition
■ rx_rmfifoempty—indicates rate match FIFO empty condition
1 The rate match FIFO status signals are not available in PIPE mode. These signals are
encoded on the pipestatus[2:0] signal in PIPE mode as specified in the PIPE
specification.
Rate Match FIFO in PCI Express (PIPE) Mode
In PIPE mode, the rate match FIFO is capable of compensating up to ± 300 PPM (total
600 PPM) difference between the upstream transmitter and the local receiver. The
PIPE protocol requires the transmitter to send SKP ordered sets during IPGs, adhering
to rules listed in the base specification. The SKP ordered set is defined as a /K28.5/
COM symbol followed by three consecutive /K28.0/ SKP symbols groups. The PIPE
protocol requires the receiver to recognize a SKP ordered set as a /K28.5/ COM
symbol followed by one to five consecutive /K28.0/ SKP symbols.
The rate match FIFO operation is compliant to PIPE Base Specification 2.0. The rate
match operation begins after the synchronization state machine in the word aligner
indicates synchronization is acquired by driving the rx_syncstatus signal high.
The rate match FIFO looks for the SKP ordered set and deletes or inserts SKP symbols
as necessary to prevent the rate match FIFO from overflowing or under-running.
The rate match FIFO inserts or deletes only one SKP symbol per SKP ordered set
received. The rate match FIFO insertion and deletion events are communicated to the
core fabric on the pipestatus[2:0] port from each channel. The
pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the
/K28.5/ COM symbol of the SKP ordered set in which the /K28.0/ SKP symbol is
inserted. The pipestatus[2:0] signal is driven to 3'b010 for one clock cycle
synchronous to the /K28.5/ COM symbol of the SKP ordered set from which the
/K28.0/ SKP symbol is deleted.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation