HC4GX15 Datasheet, PDF (90/668 Pages) Altera Corporation – HardCopy IV Device Handbook

7–24
Chapter 7: External Memory Interfaces in HardCopy IV Devices
HardCopy IV External Memory Interface Features
Figure 7–15. DQS and CQn Pins and DQS Phase-Shift Circuitry
DLL
Reference
Clock
DQS
Pin
CQn
Pin
Δt
Δt
DQS
Pin
DQS Logic
Blocks
Δt
DQS
Phase-Shift
Circuitry
to IOE
to IOE
to IOE
CQn
Pin
Δt
to IOE
DLL
Reference
Clock
DQS
Phase-Shift
Circuitry
to
IOE
DQS
Δt
to
Pin
IOE
to
IOE
CQn
Pin
Δt
to
IOE
DQS Logic
Blocks
Δt
CQn
Pin
Δt
DQS
Pin
DQS
Pin
CQn
Pin
Δt
to
IOE
Δt
to
IOE
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS
Pin
DQS
Phase-Shift
Circuitry
to IOE
to IOE
DLL
Reference
Clock
Δt
CQn
Pin
Δt
DQS
Pin
to IOE
to IOE
Δt
Δt
CQn
Pin
DQS
Pin
DQS
Phase-Shift
Circuitry
DLL
Reference
Clock
The DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated
concurrently at every DQS or CQn pin.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation