HC4GX15 Datasheet, PDF (394/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
PCI Express (PIPE) Interface
In PIPE mode, each channel has a PIPE interface block that transfers data, control, and
status signals between the PHY-MAC layer and the transceiver channel PCS and PMA
blocks. The PIPE interface block is compliant to version 2.0 of the PIPE specification. If
you use the PIPE hard IP block, the PHY-MAC layer is implemented in the hard IP
block. Otherwise, the PHY-MAC layer can be implemented using soft IP in the core
fabric.
1 The PIPE interface block is only used in PIPE mode and cannot be bypassed.
Besides transferring data, control, and status signals between the PHY-MAC layer
and the transceiver, the PIPE interface block implements the following functions
required in a PIPE-compliant physical layer device:
■ Forces the transmitter buffer in electrical idle state
■ Initiates the receiver detect sequence
■ 8B/10B encoder disparity control when transmitting compliance pattern
■ Manages the PIPE power states
■ Indicates the completion of various PHY functions; for example, receiver detection
and power state transitions on the pipephydonestatus signal
■ Encodes the receiver status and error conditions on the pipestatus[2:0] signal
as specified in the PIPE specification
Transmitter Buffer Electrical Idle
When the input signal tx_forceelecidle is asserted high, the PIPE interface block
puts the transmitter buffer in that channel in the electrical idle state. During electrical
idle, the transmitter buffer differential and common mode output voltage levels are
compliant to the PIPE Base Specification 2.0 for both PIPE Gen1 and Gen2 data rates.
Figure 1–107 shows the relationship between the assertion of the
tx_forceelecidle signal and the transmitter buffer output on the tx_dataout
port. Time T1 taken from the assertion of the tx_forceelecidle signal to the
transmitter buffer reaching electrical idle voltage levels is pending characterization.
Once in the electrical idle state, the PIPE protocol requires the transmitter buffer to
stay in electrical idle for a minimum of 20 ns for both Gen1 and Gen2 data rates.
1 The minimum period of time for which the tx_forceelecidle signal must be
asserted high such that the transmitter buffer stays in electrical idle state for at least
20 ns is pending characterization.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation