HC4GX15 Datasheet, PDF (381/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
1–117
Offset cancellation is executed automatically once each time a HardCopy IV GX
device is powered on. The control logic for offset cancellation is integrated into the
ALTGX_RECONFIG megafunction. To use this logic, you need to enable the offset
cancellation option in the ALTGX_RECONFIG MegaWizard Plug-In Manager.
Additionally, the reconfig_fromgxb and reconfig_togxb buses and the
necessary clocks need to be connected between the ALTGX instance and the
ALTGX_RECONFIG instance.
f For more information about offset cancellation control logic connectivity, refer to the
HardCopy IV GX Dynamic Reconfiguration chapter in volume 3 of the HardCopy IV
Device Handbook.
1 During offset cancellation, signified by high on the busy signal, the
rx_analogreset is not relevant until the busy signal goes low.
Offset cancellation logic requires a separate clock. In PIPE mode, you must connect
the clock input to the fixedclk port provided by the ALTGX MegaWizard Plug-In
Manager. The frequency of this clock input must be 125 MHz. For all other functional
modes, connect the clock input to the reconfig_clk port provided by the ALTGX
MegaWizard Plug-In Manager. The frequency of the clock connected to the
reconfig_clk port must be within the range of 37.5 to 50 MHz. Figure 1–99 shows
the interface of the offset cancellation control logic (ALTGX_RECONFIG instance) and
the ALTGX instance.
Figure 1–99. Interface of Offset Cancellation Control Logic to the ALTGX Instance
ALTGX_RECONFIG Instance
busy
reconfig_clk
Dynamic Re-config
logic
Offset Cancellation
Logic
reconfig_togxb
reconfig_fromgxb
ALTGX Instance with 4 Channels
Transceiver Block
TX
RX
Buffer
CDR
TX
RX
Buffer
CDR
reconfig_clk
TX
RX
Buffer
CDR
TX
RX
Buffer
CDR
The offset cancellation process begins by disconnecting the path from the receiver
input buffer to the receiver CDR. It then sets the receiver CDR into a fixed set of
dividers to guarantee a V_CO clock rate that is within the range necessary to provide
proper offset cancellation. Subsequently, the offset cancellation process goes through
various states and culminates in the offset cancellation of the receiver buffer and the
receiver CDR.
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3