HC4GX15 Datasheet, PDF (410/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–146
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCI
Express (PIPE) ×8 Mode
Figure 1–117 shows the PCI Express (PIPE) rateswitch circuitry in PIPE ×8 mode
configured at Gen2 (5 Gbps) data rate.
Figure 1–117. Dynamic Switch Signaling in PCI Express (PIPE) ×8 Mode
Slave Transceiver Block
In^IntP^Ite^nPeItnIrr^IPePtPff^PrIeaEa^PfIrcPEaEfec^Ecacee^e
pipephydonestatus
[7:4]
Transceiver
PCS
Receiver
Phase
Comp
FIFO
reset_int
Transceiver
Phase
Comp
FIFO
reset_int
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
rx_datain
rx_cruclk _{/1, /2,}
/4
Clock and Data Recovery [CDR] Unit
LTR/LTD
Controller
Phase
Detector
(PD)
Phase
/2
Frequency
Detector
(PFD)
1
0 _/2
Charge
Pump +
Loop
Filter
rateswitch_asn
VCO /L
/M
rateswitch_asn
Serial Recovered Clock
Parallel Recovered Clock
Core Fabric
PIPE
Interface
Transceiver
PCS
Receiver
Phase
Comp
FIFO
reset_int
Transceiver
Phase
Comp
FIFO
reset_int
pipephydonestatus
[3:0]
rateswitch
PCI
Express
Rate Switch
Controller
CCU
Master Transceiver Block
rx_locktorefclk
rx_locktodata
signal detect
rx_freqlocked
Clock and Data Recovery [CDR] Unit
LTR/LTD
Controller
rx_datain
Phase
Detector
(PD)
Phase
/1, /2,
/4
/2
Frequency
Detector
rx_cruclk
(PFD)
1
0 _/2
pcie_gen2switch
Charge
Pump +
Loop
Filter
VCO /L
/M
pcie_gen2switch
Serial Recovered Clock
Parallel Recovered Clock
CMU 0_Channel
pcie_gen2switch
pcie_gen2switch_done
CMU 0_PLL
/1, /2, /4
CMU 0 Clock Divider
PCI
Express
Clock
Switch
Circuitry
4, /5, /8, /10
High-Speed Serial Clock to the
eight bonded channels in the
master and slave transceiver blocks
Low-Speed Parallel Clock to the
eight bonded channels in the
master and slave transceiver blocks
CMU 1_PLL
CMU 1_Channel
CMU 1 Clock Divider
/1, /2, /4
4, /5, /8, /10
PCI Express Clock Switch Circuitry
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation