HC4GX15 Datasheet, PDF (408/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–144
Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
Table 1–39. Transceiver Clock Frequencies Signaling Rates in PCI Express (PIPE) ×4 Mode (Part 2 of 2)
Transceiver Clocks
Parallel Recovered Clock
Core Fabric-Transceiver Interface Clock
Gen1 (2.5 Gbps) to Gen2 (5 Gbps)
Switch (Low-to-High Transition on
the rateswitch Signal)
250 MHz to 500 MHz
125 MHz to 250 MHz
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
Switch (High-to-Low Transition on the
rateswitch Signal)
500 MHz to 250 MHz
250 MHz to 125 MHz
The PCI Express (PIPE) clock switch circuitry in the CMU0 clock divider block
performs the clock switch between 250 MHz and 500 MHz on the low-speed parallel
clock when switching between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rates. It
indicates successful completion of clock switch on the pcie_gen2switchdone
signal to the PIPE rateswitch controller. The PIPE rateswitch controller forwards the
clock switch completion status to the PIPE interface block. The PIPE interface block
communicates the clock switch completion status to the PHY-MAC layer by asserting
the pipephydonestatus signal of all bonded channels for one parallel clock cycle.
Figure 1–116 shows the low-speed parallel clock switch between Gen1 (250 MHz) and
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch
signal. The rateswitch completion is shown marked with a one clock cycle assertion of
the pipephydonestatus signal of all bonded channels.
1 Time T1 from a transition on the rateswitch signal to the assertion of
pipephydonestatus is pending characterization.
Figure 1–116. Low-Speed Parallel Clock Switching in PCI Express (PIPE) ×4 Mode
Low-Speed Parallel Clock
250 MHz (Gen1)
500 MHz (Gen2)
250 MHz (Gen1)
rateswitch
pipephydonestatus[3]
pipephydonestatus[0]
T1
T1
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation