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HC4GX15 Datasheet, PDF (129/668 Pages) Altera Corporation – HardCopy IV Device Handbook
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Pin Placement Guidelines
8–19
Figure 8–19. Center Left/Right PLLs Driving DPA-Enabled Differential I/Os
Maximum 26 channels
driven by the center
left/right PLL
Maximum 26 channels
driven by the center
left/right PLL
Corner
Left/Right PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
Center
Left/Right PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Corner
Left/Right PLL
Corner
Left/Right PLL
Reference
CLK
DPA-enabled
Diff I/O
Maximum 26 channels
driven by the upper center
left/right PLL
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
Center
Left/Right PLL
Maximum 26 channels
driven by the upper center
left/right PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Corner
Left/Right PLL
Maximum 26 channels
driven by the upper center
left/right PLL
One Unused
Channel for Buffer
Maximum 26 channels
driven by the upper center
left/right PLL
If the top PLL_L2/PLL_R2 drives DPA-enabled channels in the lower differential
bank, the PLL_L3/PLL_R3 cannot drive DPA-enabled channels in the upper
differential banks and vice versa. In other words, the center left or right PLLs cannot
drive cross-banks simultaneously, as shown in Figure 8–20.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1