HC4GX15 Datasheet, PDF (353/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–89
Receiver Channel Datapath
When the rx_revbitordwa signal is driven high in Basic double-width mode, the
16-bit or 20-bit data D[15:0] or D[19:0] at the output of the word aligner gets
rewired to D[0:15] or D[0:19], respectively.
Flipping the parallel data using this feature allows the receiver to forward the correct
bit-ordered data to the core fabric on the rx_dataout port in the case of
MSBit-to-LSBit transmission.
Figure 1–66 shows the receiver bit reversal feature in Basic single-width 10 bit wide
datapath configurations.
Figure 1–66. Receiver Bit Reversal in Single-Width Mode
D[9]
D[0]
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5]
D[4]
rx_revbitordwa = high
D[4]
D[5]
D[3]
D[6]
D[2]
D[7]
D[1]
D[8]
D[0]
Output of Word Aligner before
RX bit reversal
D[9]
Output of Word Aligner after RX
bit reversal
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3