HC4GX15 Datasheet, PDF (372/668 Pages) Altera Corporation – HardCopy IV Device Handbook

1–108
Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Figure 1–91 shows a 20-bit code group decoded into 16-bit data and 2-bit control
identifier by the 8B/10B decoder in double-width mode.
Figure 1–91. 8B/10 Decoder in 20-Bit Double-Width Mode
j¹ h¹ g¹ f¹ i¹ e¹ d¹ c¹ b¹ a¹ j
hg
f
i
edc
ba
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
Cascaded 8B/10B Conversion
CTRL[1..0] 15 14 13 13 11 10 9 8 7 6
H¹ G¹ F¹ E¹ D¹ C¹ B¹ A¹ H G
543
FE D
21
CB
0 Parallel Data
A
Control Code Group Detection
The cascaded 8B/10B decoder indicates whether the decoded 16-bit code group is a
data or control code group on the 2-bit rx_ctrldetect[1:0] port. The
rx_ctrldetect[0] signal is driven high or low depending on whether decoded
data on the rx_dataout[7:0] port (LSByte) is a control or data code group,
respectively. The rx_ctrldetect[1] signals are driven high or low depending on
whether decoded data on the rx_dataout[15:8] port (MSByte) is a control or data
code group, respectively.
Figure 1–92 shows the 8B/10B decoding of the received 10-bit /K28.5/ control code
group into 8-bit data code group (8'hBC) driven on the rx_dataout port. The
rx_ctrldetect signal is asserted high synchronous with 8'hBC on the
rx_dataout port, indicating that it is a control code group. The rest of the codes
received are data code groups /Dx.y/.
Figure 1–92. 8B/10B Decoder 10-Bit Control Code Group
clock
datain[19:10]
datain[9:0]
D3.4
D24.3
D28.5
D28.5
D15.0
D15.0
D3.4
D3.4
rx_ctrldetect[1:0]
00
01
00
rx_dataout[15:0] 16'h8378 16'hBCBC 16'h0F0F 16'h8383
Byte Deserializer
The core fabric-transceiver interface frequency has an upper limit of 250 MHz. In
functional modes that have a receiver PCS frequency greater than 250 MHz, the
parallel received data and status signals cannot be forwarded directly to the core
fabric because it violates the upper limit of the 250 MHz core fabric-transceiver
interface frequency. In such configurations, the byte deserializer is required to reduce
the core fabric-transceiver interface frequency to half while doubling the parallel data
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation