HC4GX15 Datasheet, PDF (476/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–18
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic
Table 2–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 8 of 9)
Port Name
Input/
Output
Description
Transceiver Channel Reconfiguration Control/Status Signals
reconfig_mode_sel[2:0]
Input
Set the following values at this signal to activate the appropriate
dynamic reconfiguration mode:
3’b000 – PMA controls reconfiguration mode. This is the default
value.
3’b011 – Data Rate Division in TX mode
3’b100 – CMU PLL reconfiguration mode
3’b101 – Channel and CMU PLL reconfiguration mode
3’b110 – Channel reconfiguration with TX PLL select mode
3’b111 – Not supported
reconfig_address_out[5:0]
Output
This signal is always available for you to select in the Channel and
TX PLL reconfiguration screen. This signal is applicable only in the
dynamic reconfiguration modes grouped under Channel and TX
PLL select/reconfig option.
This signal represents the current address used by the
ALTGX_RECONFIG instance when writing the .mif into the
transceiver channel. This signal increments by 1, from 0 to last
address, then starts at 0 again. You can use this signal to indicate
the end of all the .mif write transactions
(reconfig_address_out[5:0] changes from the last
address to 0 at the end of all the .mif write transactions).
reconfig_address_en
Output
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
The dynamic reconfiguration controller asserts
reconfig_address_en to indicate that
reconfig_address_out[5:0] has changed. This signal
gets asserted only after the dynamic reconfiguration controller
completes writing one 16-bit word of the .mif.
reset_reconfig_address
Input
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
Enable this signal and assert it for one reconfig_clk clock
cycle if you want to reset the reconfiguration address used by the
ALTGX_RECONFIG instance during reconfiguration.
reconfig_data[15:0]
Input
This signal is applicable only in the dynamic reconfiguration modes
grouped under the Channel and TX PLL select/reconfig option.
This is a 16-bit word carrying the reconfiguration information. It is
stored in a .mif file that you need to generate. The
ALTGX_RECONFIG instance requires that you provide
reconfig_data [15:0]on every .mif write transaction using
the write_all signal.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation