HC4GX15 Datasheet, PDF (401/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–137
Table 1–36. Electrical Idle Inference Conditions (Part 2 of 2)
LTSSM State
Recovery.Speed when
successful speed negotiation
= 1'b1
Recovery.Speed when
successful speed negotiation
= 1'b0
Loopback.Active
(as slave)
Gen1 (2.5 Gbps)
Gen2 (5 Gbps)
rx_elecidleinfersel[2:0]
Absence of TS1 or TS2
Absence of TS1 or TS2
ordered set in 1280 UI interval ordered set in 1280 UI window
3'b101
Absence of an exit from
Electrical Idle in 2000 UI
interval
Absence of an exit from
Electrical Idle in 128 μs
window
Absence of an exit from
Electrical Idle in 16000 UI
interval
—
3'b110
3'b111
In the Recovery.Speed substate of the LTSSM state machine with unsuccessful speed
negotiation (rx_elecidleinfersel[2:0] = 3'b110), the PCI Express (PIPE) Base
Specification requires the receiver to infer an electrical idle condition
(pipeelecidle = high) if absence of an exit from Electrical Idle is detected in a
2000 UI interval for Gen1 data rate and 16000 UI interval for Gen2 data rate. The
electrical idle inference module detects an absence of exit from Electrical Idle if four
/K28.5/ COM code groups are not received in the specified interval.
In other words, when configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b110, the Electrical Idle Inference module asserts
pipeelecidle high if it does not receive four /K28.5/ COM code groups in a
2000 UI interval. When configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b111 in the Loopback Active substate of the
LTSSM state machine, the Electrical Idle Inference module asserts pipeelecidle
high if it does not receive four /K28.5/ COM code groups in a 128 μs interval.
When configured for Gen2 data rate and rx_elecidleinfersel[2:0] = 3'b110,
the Electrical Idle Inference module asserts pipeelecidle high if it does not receive
four /K28.5/ COM code groups in a 16000 UI interval.
1 The Electrical Idle Inference module does not have the capability to detect the
electrical idle exit condition based on reception of the electrical idle exit ordered set
(EIEOS), as specified in the PCI Express (PIPE) Base Specification.
If you select the Enable Electrical Idle Inference Functionality option in the ALTGX
MegaWizard Plug-In Manager and drive rx_elecidleinfersel[2:0] =
3'b0xx, the Electrical Idle Inference block uses the EIOS detection from the Fast
Recovery circuitry to drive the pipeelecidle signal.
If you do not select the Enable electrical idle inference functionality option in the
ALTGX MegaWizard Plug-In Manager, the Electrical Idle Inference module is
disabled. In this case, the rx_signaldetect signal from the signal detect circuitry in
the receiver buffer is inverted and driven as the pipeelecidle signal.
PCI Express (PIPE) Gen2 (5 Gbps) Support
The PCI Express (PIPE) functional mode supports the following additional features
when configured for 5 Gbps data rate:
■ Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3