HC4GX15 Datasheet, PDF (407/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–143
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCI
Express (PIPE) ×4 Mode
Figure 1–115 shows the PIPE rateswitch circuitry in PIPE ×4 mode configured at Gen2
(5 Gbps) data rate.
Figure 1–115. Dynamic Switch Signaling in PCI Express (PIPE) ×4 Mode
Core
Fabric
Transceiver Block
Transceiver PCS
rx_locktorefclk
rx_locktodata
signal_detect
rx_freqlocked
LTR/LTD
Controller
Clock and Data Recovery (CDR) Unit
Receiver
1
Phase
PIPE
Compen-
sation
FIFO
reset_int
rx_datain
Phase
Detector
(PD)
0
/2
pcie_gen2switch
In_InIt_ne_IPtnPetr_eIPtf_rPIa_efrPaIfrc_EPafEce_acEecee
Transmitter
Phase
Compen-
sation
Charge
Pump
+
Loop Filter
VCO
/L
FIFO
reset_int
rx_cruclk
/1. /2,
/4
/2
Phase
Frequency
Detector
(PFD)
/M
pcie _gen2switch
Serial Recovered Clock
Parallel Recovered Clock
pipephydonestatus[3:0]
rateswitch
PCI
Express
Rate Switch
Controller
CCU
CMU0_
PLL
pcie_gen2switch
pcie_gen2switch_done
/1, /2, /4
CMU0_Channel
PCI
Express
Clock
Switch
Circuitry
CMU0 Clock Divider
/4, /5, /8, /10
High-Speed Serial Clock to the
four (PIPE x4) bonded channels
Low-Speed Parallel Clock to the
four (PIPE x4) bonded channels
CMU1_
PLL
/1, /2, /4
CMU1_Channel
CMU1 Clock Divider
/4, /5, /8, 10
PCI Express Clock Switch Circuitry
In PIPE ×4 mode configured at Gen2 (5 Gbps) data rate, when the PIPE rateswitch
controller sees a transition on the rateswitch signal, it sends the
pcie_gen2switch control signal to the PIPE clock switch circuitry in the CMU0 clock
divider block and the receiver CDR to switch to the instructed signaling rate. A
low-to-high transition on the rateswitch signal initiates a Gen1 (2.5 Gbps) to Gen2
(5 Gbps) signaling rateswitch. A high-to-low transition on the rateswitch signal
initiates a Gen2 (5 Gbps) to Gen1 (2.5 Gbps) signaling rateswitch.
Table 1–39 shows the transceiver clock frequencies when switching between 2.5 Gbps
and 5 Gbps signaling rates.
Table 1–39. Transceiver Clock Frequencies Signaling Rates in PCI Express (PIPE) ×4 Mode (Part 1 of 2)
Transceiver Clocks
High-Speed Serial Clock
Low-Speed Parallel Clock
Serial Recovered Clock
Gen1 (2.5 Gbps) to Gen2 (5 Gbps)
Switch (Low-to-High Transition on
the rateswitch Signal)
1.25 GHz to 2.5 GHz
250 MHz to 500 MHz
1.25 GHz to 2.5 GHz
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
Switch (High-to-Low Transition on the
rateswitch Signal)
2.5 GHz to 1.25 GHz
500 MHz to 250 MHz
2.5 GHz to 1.25 GHz
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3