HC4GX15 Datasheet, PDF (72/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 7: External Memory Interfaces in HardCopy IV Devices
Memory Interfaces Pin Support
Memory Interfaces Pin Support
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM) pins to enable write masking and QVLD pins to indicate that the read data
is ready to be captured. This section describes how HardCopy IV devices support
these pins.
Data and Data Clock/Strobe Pins
HardCopy IV DDR memory interface read data-strobes or clocks are called DQS pins.
Depending on the memory specifications, the DQS pins can be bidirectional
single-ended signals (in DDR2 and DDR SDRAM), bidirectional differential signals
(DDR3 and DDR2 SDRAM), unidirectional differential signals (in RLDRAM II), or
unidirectional complementary signals (QDRII+ and QDRII SRAM). Connect the
unidirectional read and write data-strobes or clocks to HardCopy IV DQS pins.
HardCopy IV devices offer differential input buffers for differential read
data-strobe/clock operations and provide an independent DQS logic block for each
CQn pin for complementary read data-strobe/clock operations. In the HardCopy IV
pin tables, the differential DQS pin-pairs are denoted as DQS and DQSn pins; the
complementary DQS signals are denoted as DQS and CQn pins. DQSn and CQn pins
are marked separately in the pin table. Each CQn pin connects to a DQS logic block
and the shifted CQn signals go to the negative-edge input registers in the DQ IOE
registers.
1 Use differential DQS signaling for DDR2 SDRAM interfaces running higher than
333 MHz.
HardCopy IV DDR memory interface data pins are called DQ pins. The DQ pins can
be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and RLDRAM II
common I/O (CIO) interfaces, or unidirectional signals, as in QDRII+, QDRII SRAM,
and RLDRAM II separate I/O (SIO) devices. Connect the unidirectional read data
signals to HardCopy IV DQ pins and the unidirectional write data signals to a
DQS/DQ group other than the read DQS/DQ group. Furthermore, the write clocks
must be assigned to the DQS/DQSn pins associated with this write DQS/DQ group.
Do not use the DQS/CQn pin-pair for write clocks.
1 Using a DQS/DQ group for the write data signals minimizes output skew and allows
access to the write leveling circuitry (for DDR3 SDRAM interfaces). These pins also
have access to deskewing circuitry that can compensate for delay mismatch between
signals on the bus.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation