HC4GX15 Datasheet, PDF (286/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
CMU Channels
CMU Channels
The HardCopy IV GX device contains two CMU channels—the CMU0 and CMU1
channels—within each transceiver block. The CMU channels can be configured as a
transceiver channel or as a clock generation block. The building blocks used in the
CMU channels to achieve this are described below. Each CMU channel contains a
CMU PLL that provides clocks to the transmitter channels within the same
transceiver block.
Configuring CMU Channels for Clock Generation
The CMU0 channel has additional capabilities to support bonded protocol functional
modes such as Basic ×4, XAUI, and PCI Express (PIPE). You can select these
functional modes from the ALTGX MegaWizard Plug-In Manager. You can enable
Basic ×4 functional mode in the ALTGX MegaWizard Plug-In Manager by selecting
the ×4 option in Basic mode.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation