HC4GX15 Datasheet, PDF (663/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: DC and Switching Characteristics of HardCopy IV Devices
Glossary
Table 1–39. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
J
HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications are in the following figure:
TMS
TDI
J _{JTAG Timing}
Specifications
TCK
TDO
t_JCP
t _JCH
t _JCL
t_JPZX
t _JPSU
t_JPCO
t _JPH
t _JPXZ
K
—
—
L
—
—
M
—
—
N
—
—
O
—
—
The following block diagram highlights the PLL specification parameters:
Diagram of PLL Specifications (1)
P
PLL
Specifications
CLK
Core Clock
Switchover
fIN
fINPFD
N
PFD
CP
LF
VCO fVCO
CLKOUT Pins
fOUT_EXT
Counters
C0..C9
fOUT
GCLK
Key
Reconfigurable in User Mode
M
External Feedback
RCLK
Q
—
R
RL
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
—
Receiver differential input discrete resistor (external to HardCopy IV device).
1–33
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 4