HC4GX15 Datasheet, PDF (342/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV GX Transceiver Architecture
Receiver Channel Datapath
Automatic Synchronization State Machine Mode Word Aligner with 10-Bit
PMA-PCS Interface Mode
Protocols such as PCI Express (PIPE), XAUI, Gigabit Ethernet, and Serial RapidIO
require the receiver PCS logic to implement a synchronization state machine to
provide hysteresis during link synchronization. Each of these protocols defines a
specific number of synchronization code groups that the link must receive to acquire
synchronization and a specific number of erroneous code groups that it must receive
to fall out of synchronization.
In PIPE, XAUI, Gigabit Ethernet, and Serial RapidIO functional modes, the Quartus II
software configures the word aligner in automatic synchronization state machine
mode. It automatically selects the word alignment pattern length and pattern as
specified by each protocol. In each of these functional modes, the protocol-compliant
synchronization state machine is implemented in the word aligner.
In Basic single-width functional mode with 10-bit PMA-PCS interface, you can
configure the word aligner in automatic synchronization state machine mode by
selecting the Use the built-in synchronization state machine option in the ALTGX
MegaWizard Plug-In Manager. It also allows you to program a custom 7-bit or 10-bit
word alignment pattern that the word aligner uses for synchronization.
1 The 10-bit input data to the word aligner configured in automatic synchronization
state machine mode must be 8B/10B encoded.
Table 1–21 shows the synchronization state machine parameters that the Quartus II
software allows in supported functional modes. The synchronization state machine
parameters are fixed for PIPE, XAUI, GIGE, and Serial RapidIO modes as specified by
the respective protocol. For Basic single-width mode, you can program these
parameters as suited to your proprietary protocol implementation.
Table 1–21. Synchronization State Machine Functional Modes
Functional Mode
Basic
PCI Express
Serial Single-Width
(PIPE)
XAUI
GIGE
RapidIO
Mode
Number of valid synchronization code groups or
4
ordered sets received to achieve synchronization
4
3
127
1 to 256
Number of erroneous code groups received to lose
17
synchronization
4
4
3
1 to 64
Number of continuous good code groups received
16
to reduce the error count by one
4
4
255
1 to 256
After de-assertion of the rx_digitalreset signal in automatic synchronization
state machine mode, the word aligner starts looking for the word alignment pattern or
synchronization code groups in the received data stream. When the programmed
number of valid synchronization code groups or ordered sets is received, the
rx_syncstatus signal is driven high to indicate that synchronization is acquired.
The rx_syncstatus signal is constantly driven high until the programmed number
of erroneous code groups is received without receiving intermediate good groups;
after which the rx_syncstatus is driven low. The word aligner indicates loss of
synchronization (rx_syncstatus remains low) until the programmed number of
valid synchronization code groups are received again.
HardCopy IV Device Handbook Volume 3
© June 2009 Altera Corporation