HC4GX15 Datasheet, PDF (125/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices Differential Data Orientation
8–15
Figure 8–15. Clocks in HardCopy IV and Stratix IV Devices with Center and Corner PLLs
Corner
PLL_L1
2
LVDS DPA
4 Clock Clock
Network Network
4
2
Center
PLL_L2
2
Center
PLL_L3
4
LVDS DPA
4 _{Clock Clock}
Network Network
2
Corner
PLL_L4
Quadrant
Quadrant
Quadrant
Quadrant
Corner
PLL_R1
2
DPA LVDS
Clock Clock 4
Network Network
4
Center ₂
PLL_R2
2
Center
PLL_R3
4
DPA LVDS
Clock Clock ⁴
Network Network
2
Corner
PLL_R4
High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For
operation at 1 Gbps with a SERDES factor of 10, the external clock is multiplied by 10,
and phase-alignment is set in the PLL to coincide with the sampling window of each
data bit. The data is sampled on the falling edge of the multiplied clock. Figure 8–16
shows the data bit orientation of the ×10 mode.
Figure 8–16. Bit Orientation in Quartus II Software Differential I/O Bit Position
inclock/outclock
data in
MSB
10 LVDS Bits
LSB
9 87 6543210
Data synchronization is necessary for successful data transmission at high
frequencies. Figure 8–17 shows the data bit orientation for a channel operation. This
figure is based on the following:
■ SERDES factor equals clock multiplication factor
■ Edge alignment is selected for phase alignment
■ Implemented in hard SERDES
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1