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| HC4GX15 Datasheet, PDF (80/668 Pages) Altera Corporation – HardCopy IV Device Handbook | |||
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7â14
Chapter 7: External Memory Interfaces in HardCopy IV Devices
Memory Interfaces Pin Support
Figure 7â7. Number of DQS/DQ Groups per Bank in HC4E35L and HC4E35F Devices in a 1517-pin FineLine BGA Package
DLL1
I/O Bank 8A (1)
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 1A (1)
50 User I/Os (2)
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 1C
42 User I/Os (2)
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 2C
42 User I/Os (2)
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 2A (1)
50 User I/Os (2)
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
DLL2
I/O Bank 3A (1)
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 8B
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 8C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
Ã32/Ã36=0
I/O Bank 7C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
Ã32/Ã36=0
1517-Pin FineLine BGA
I/O Bank 3B
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 3C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
Ã32/Ã36=0
I/O Bank 4C
32 User I/Os
Ã4=3
Ã8/Ã9=1
Ã16/Ã18=0
Ã32/Ã36=0
I/O Bank 7B
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 4B
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 7A (1)
48 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
DLL4
I/O Bank 6A (1)
50 User I/Os (2)
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 6C
42 User I/Os (2)
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 5C
42 User I/Os (2)
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 5A (1)
50 User I/Os (2)
Ã4=7
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 4A (1)
48 User I/Os
Ã4=8
x8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
DLL3
Notes to Figure 7â7:
(1) You can use the DQS/DQSn pins in some of the Ã4 groups as RUP/RDN pins. You cannot use a Ã4 group for memory interfaces if two pins in the
group are used as RUP and RDN pins for OCT calibration. You can still use the Ã16/Ã18 or Ã32/Ã36 groups including the Ã4 groups. However, there
are restrictions on using Ã8/Ã9 groups that include these Ã4 groups.
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight
dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn,
PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation
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