HC4GX15 Datasheet, PDF (112/668 Pages) Altera Corporation – HardCopy IV Device Handbook

8–2
Chapter 8: High-Speed Differential I/O Interfaces and DPA in HardCopy IV Devices
I/O Banks
Figure 8–1. I/O Banks in HardCopy IV E Devices (Note 1), (2), (3), (4), (5), (6)
PLL_L1 Bank 8A
Bank 8B
Bank 8C PLL_T1 PLL_T2 Bank 7C
Bank 7B
Bank 7A PLL_R1
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operations
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operations
PLL_L2
PLL_L3
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operations
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15 Class II,
differential HSTL-12 Class II standards are only supported
for input operations
PLL_R2
PLL_R3
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operations
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operations
PLL_L4 Bank 3A
Bank 3B
Bank 3C _{PLL_B1 PLL_B2} Bank 4C
Bank 4B
Bank 4A PLL_R4
Notes to Figure 8–1:
(1) The 1152- and 1517-pin packages have 20 I/O banks. The 780-pin package has 16 I/O banks.
(2) Figure 8–1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. For exact
locations, refer to the pin list and Quartus II software.
(3) Differential HSTL and SSTL I/Os use two single-ended outputs with the second output programmed as inverted for the transmitter and uses a true
SSTL/HSTL differential input buffer for the receiver.
(4) Top and bottom I/O differential HSTL and SSTL inputs use LVDS differential input buffers without on-chip differential termination support.
(5) Top and bottom I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(6) The PLL blocks are shown for location purposes only and are not considered additional banks. The PLL input and output uses the I/Os in adjacent
banks.
HardCopy IV Device Handbook, Volume 1
© January 2010 Altera Corporation