HC4GX15 Datasheet, PDF (403/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
Functional Modes
1–139
PCI Express (PIPE) Rateswitch Controller
The rateswitch signal serves as the input signal to the PCI Express (PIPE)
rateswitch controller. After seeing a transition on the rateswitch signal from the
PHY-MAC layer, the PCI Express (PIPE) rateswitch controller performs the following
operations:
■ Controls the PIPE clock switch circuitry to switch between Gen1 (2.5 Gbps) and
Gen2 (5 Gbps) signaling rate, depending on the rateswitch signal level
■ Disables and resets the transmitter and receiver phase compensation FIFO
pointers until the PIPE clock switchover circuitry indicates successful rateswitch
completion
■ Communicates completion of rateswitch to the PIPE interface module, which in
turn communicates completion of the rateswitch to the PHY-MAC layer on the
pipephydonestatus signal
PCI Express (PIPE) rateswitch controller location:
■ In PIPE ×1 mode, the PIPE rateswitch controller is located in the transceiver PCS of
each channel.
■ In PIPE ×4 mode, the PIPE rateswitch controller is located in CMU0 Channel
within the transceiver block.
■ In PIPE ×8 mode, the PIPE rateswitch controller is located in CMU0_Channel
within the master transceiver block.
1 When operating at the Gen 2 data rate, asserting the rx_digitalreset signal
causes the PIPE rateswitch circuitry to switch the transceiver to Gen 1 data rate.
1 When switching from Gen1 to Gen2 using the dynamic reconfiguration controller,
you must set the two ports of the dynamic reconfiguration controller, tx_preemp_0t
and tx_preemp_2t, to zero to meet the Gen2 de-emphasis specifications. When
switching from Gen2 to Gen1, if your system requires specific settings on
tx_preemp_01 and tx_preemp_2t, those values must to be set at the respective
two ports of the dynamic reconfiguration controller to meet your system
requirements.
PCI Express (PIPE) Clock Switch Circuitry
When the PHY-MAC layer instructs a rateswitch between the Gen1 (2.5 Gbps) and
Gen2 (5 Gbps) signaling rates, both the transmitter high-speed serial and low-speed
parallel clock and the CDR recovered clock must switch to support the instructed data
rate. HardCopy IV GX transceivers have dedicated PIPE clock switch circuitry located
in the following blocks:
■ Local clock divider in transmitter PMA of each transceiver channel
■ CMU0 clock divider in CMU0_Channel of each transceiver block
■ Receiver CDR in receiver PMA of each transceiver channel
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3