HC4GX15 Datasheet, PDF (570/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2–112
Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–53 shows the required signal transitions to reconfigure the CMU PLL
with a logical tx pll value of 1. Keep the logical_tx_pll_sel and
logical_tx_pll_sel_en signals at a constant logic level until the dynamic
reconfiguration controller asserts the channel_reconfig_done signal.
Figure 2–53. Signal Transition to Reconfigure a Transmitter PLL with a Reference Index Value of 1
Dynamic reconfiguration
controller does not register the
logical_tx_pll_sel value for this
write because the
logical_tx_pll_sel_en is low
logical_tx_pll_sel_en
logical_tx_pll_sel[1:0]
write_all
channel_reconfig_done
reconfig_mode_sel[2:0]
100
■ Condition 2: You need to reuse the .mif created for one CMU PLL on the other
CMU PLL of the same transceiver block. Consider the following ALTGX settings:
■ The main PLL in the General screen is configured to switch from 2 Gbps to
3.125 Gbps. You have assigned a logical reference index of 1 for this main PLL
(CMU0 PLL).
■ You generate a .mif for these settings.
■ The logical tx pll value stored in the .mif is 1.
■ You want to reuse the same .mif to reconfigure CMU1 PLL instead (your
intention is to switch both CMU PLLs in the transceiver block to 3.125 Gbps).
However, the logical reference index stored in the .mif is 1 (applicable only to
CMU0 PLL). You need to overwrite this logical tx pll value of 1 stored in the .mif
with the logical reference index of CMU1 PLL.
■ You can achieve this by using logical_tx_pll_sel and
logical_tx_pll_sel_en and by setting logical_tx_pll_sel = 1'b0 (logical
reference index of CMU1 PLL) and logical_tx_pll_sel_en = 1'b1.
■ By doing so, the dynamic reconfiguration controller writes the .mif contents to
CMU1 PLL (the logical reference index of this PLL is automatically 0 when you
set the logical reference index of CMU0 PLL as 1).
The following section describes when to re-use the .mif generated for one CMU PLL
on another CMU PLL, during the various dynamic reconfiguration modes.
HardCopy IV Device Handbook, Volume 3
© June 2009 Altera Corporation