HC4GX15 Datasheet, PDF (57/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 6: HardCopy IV Device I/O Features
6–7
HardCopy IV I/O
Figure 6–2 shows HardCopy IV GX devices I/O bank.
Figure 6–2. HardCopy IV GX Devices I/O Bank (Note 1), (2), (3), (4), (5), (6), (7), (8), (9), (10), (11), (12)
Bank 8A
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15 Class II,
differential HSTL-12 Class II standards are only supported
for input operations
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation
Bank 3A
Bank 3B
Bank 3C
Bank 4C
Bank 4B
Bank 4A
Notes to Figure 6–2:
(1) HC4GX15 devices do not have I/O Banks 5A, 5B, 5C, 6A, 6B, and 6C and have only two HSSI Quads on the right (GXBR1 and GXBR2).
(2) HC4GX25 devices have two HSSI Quads on the right and left (GXBL1, GXBL2, GXBR1, and GXBR2).
(3) HC4GX35 devices have three HSSI Quads on the right and left (GXBL0, GXBL1, GXBL2, GXBR0, GXBR1, and GXBR2).
(4) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(5) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(6) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(7) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(8) Clock inputs on column I/O are powered by V_CCCLKIN when configured as differential clock input. They are powered by V_CCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank V_CCIO.
(9) Row I/O banks support the dedicated LVDS output buffer.
(10) Column and row I/O banks support LVPECL standards for input clock operation.
(11) Single-ended inputs and outputs are not allowed when true differential I/O (DPA and non-DPA) exist in an I/O bank.
(12) Figure 6–2 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
© January 2010 Altera Corporation
HardCopy IV Device Handbook, Volume 1