HC4GX15 Datasheet, PDF (197/668 Pages) Altera Corporation – HardCopy IV Device Handbook

2. HardCopy Design Center
Implementation Process
HIV52002-1.0
This chapter discusses the HardCopy^® IV back-end design flow executed by the
Altera^® HardCopy Design Center when developing your HardCopy IV device.
HardCopy IV Back-End Design Flow
This section outlines the back-end design process for HardCopy IV devices.
Figure 2–1 illustrates these steps. The design process uses both proprietary and
third-party EDA tools.
Figure 2–1. HardCopy IV Back-End Design Flow
Quartus II Netlist
Formal
Verification
Clock Insertion
DFT Insertion
Global Signal Insertion
Other Tasks
Design Database
Design Database Contents:
Quartus II Constraints:
-Timing Constraints
-Placement Constraints
-Routing Constraints
HardCopy IV Design Libraries:
-Physical and Timing Models
-Base Layout Database
Processed Netlist
Timing and SI Driven
Place and Route
Formal
Verification
Netlist Signoff
Post Place
and Route Netlist
Stratix IV
Physical
Netlist
DRC/LVS/Antenna
Physical Layout
Verification
Layout Signoff
Stratix IV
.sof File
Layout GDS2
Parasitic
Extraction
Crosstalk, Sl,
Static Timing
Analysis
Timing ECO (1)
Design Tape-Out
Note to Figure 2–1
(1) Refer to Figure 2–2 for more information about the timing ECO.
Timing Signoff
Design Netlist Generation
For HardCopy IV designs, the Quartus^® II software generates a complete Verilog
gate-level netlist of your design. The HardCopy Design Center uses the netlist to start
the back-end process. In addition to the Verilog gate-level netlist, the Quartus II
software generates information as part of the design database submitted by you to the
Altera HardCopy Design Center. This information includes timing constraints,
placement constraints, and global routing information. Generation of this database
provides the HardCopy Design Center with the necessary information to complete
the design of your HardCopy IV device.
© December 2008 Altera Corporation
HardCopy IV Device Handbook, Volume 2