HC4GX15 Datasheet, PDF (245/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 4: Matching Stratix IV Power and Configuration Requirements with HardCopy IV Devices
4–11
Examples of Mapping a Stratix FPGA Configuration to a HardCopy ASIC
Figure 4–9 shows how the first Stratix IV device is replaced by a HardCopy IV device.
In this case, the microprocessor code must be modified to send configuration data
only to the second device (the Stratix IV device) of the configuration chain. The
microprocessor can only send this data after its nCE pin is asserted by the first device
(the HardCopy IV device).
Figure 4–9. Replacement of the First FPGA in the FPP Configuration Chain with a HardCopy IV Device (Note 1)
Memory
ADDR DATA[7..0]
External Host
(MAX II Device or
Microprocessor)
VCCPGM (1) V_CCPGM (1)
10 kΩ
10 kΩ
GND
HardCopy IV Device
MSEL[2..0]
CONF_DONE
nSTATUS
GND
nCE
nCEO N.C.
DATA[7..0] (2)
nCONFIG
DCLK
GND
Stratix IV Device
MSEL[2..0] (2)
CONF_DONE
nSTATUS
GND
nCE
nCEO N.C.
DATA[7..0]
nCONFIG
DCLK
Notes to Figure 4–9:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain. The V_CCPGM voltage meets the I/O
standard’s V_IH specification on the device and the external host.
(2) The DATA[7..0] and MSEL[2:0] pins are not used on the HardCopy IV device but they preserve the pin assignment and direction from the
Stratix IV device, allowing drop-in replacement.
HardCopy IV Device Replacing an FPGA Configured in a JTAG Chain
In this example, the circuit connectivity is maintained and there are no changes made
to the board. You must modify the microprocessor code so that it treats the HardCopy
IV device as a non-configurable device. The microprocessor can achieve this by
issuing a BYPASS instruction to the HardCopy IV device. With the HardCopy IV
device in BYPASS mode, the configuration data passes through it to the downstream
FPGAs.
Figure 4–10 shows an example where there are multiple FPGAs. These devices are
connected using the JTAG I/O pins for each device and programmed using the JTAG
port. An on-board microprocessor generates the configuration data.
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 2