HC4GX15 Datasheet, PDF (176/668 Pages) Altera Corporation – HardCopy IV Device Handbook

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Chapter 1: HardCopy IV Design Flow Using the Quartus II Software
Clock and PLL Planning
Although the memory in HardCopy IV devices supports the same memory functions
and features as Stratix IV devices, you cannot pre-load or initialize HardCopy IV
memory blocks with a Memory Initialization File (.mif) when they are used as RAM.
Unlike Stratix IV devices, HardCopy IV devices do not have device configuration.
The memory content of HardCopy IV devices are random after power-up. Therefore,
you must ensure that your Stratix IV design does not require a .mif if the memory
blocks are used as RAM. However, if the HardCopy IV memory block is designed as
ROM, it powers up with the ROM contents.
1 Use the ALTMEM_INIT megafunction to initialize the RAM after power-up for
HardCopy IV devices. This megafunction reads from an internal ROM (inside the
megafunction) or an external ROM (on-chip or off-chip) and writes to the RAM after
power-up.
When using non-registered output mode for the HardCopy IV MLABs, the output
powers up with memory content. When using registered output mode for these
memory blocks, the outputs are cleared on power-up. You must take this into
consideration when designing logic that might evaluate the initial power-up values of
the MLAB memory block.
f For more information about memory blocks in HardCopy IV devices, refer to the
TriMatrix Embedded Memory Blocks in HardCopy IV Devices chapter.
DSP Blocks Implementation
The Quartus II software uses a library of pre-characterized HCell macros to place
Stratix IV DSP configurations into the HardCopy IV HCell-based logic fabric.
Depending on the Stratix IV DSP configurations, the Quartus II software partitions
the DSP function into a combination of DSP HCell macros in the HardCopy IV device.
This optimizes the DSP function and allows the core fabric to be used more efficiently.
f For more information about DSP blocks in HardCopy IV devices, refer to the DSP
Block Implementation in HardCopy IV Devices chapter.
Clock and PLL Planning
To ensure that you map the Stratix IV design to a HardCopy IV design successfully,
follow these guidelines when implementing your design. They can help make your
design robust, ensuring it meets timing closure and achieves the performance you
need.
f For more information about the clock scheme and PLL features in HardCopy IV
devices, refer to the Clock Networks and PLLs in HardCopy IV Devices chapter.
Clock Networks and PLL Resources
You must consider the system clocking scheme, timing requirements, and fan-out
requirements during clock networks and PLL resources planning. Matching PLL
resources between Stratix IV and HardCopy IV devices is determined by the design’s
clocking scheme and timing requirements. For high fan-out signals, use a dedicated
clock resource.
HardCopy IV Device Handbook, Volume 2
© January 2010 Altera Corporation