HC4GX15 Datasheet, PDF (577/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 2: HardCopy IV GX Dynamic Reconfiguration
Description of Transceiver Channel Reconfiguration Modes
Figure 2–54. Input Reference Clocks Connections to the Transceiver Channels
Based on what you have set up
as the input clock source for
CMU0 PLL, this clock mux
selects the corresponding input
clock source for CMU0 PLL.
Refclk0
(Identification
number = 2)
156 .25 MHz
125MHz
Refclk1
(Identification
number = 1)
clock
mux
CMU Channels
3.125 Gbps
CMU0 PLL
clock
mux
1 Gbps
CMU1 PLL
full duplex transceiver channel 1
TX CHANNEL 1
Logical
TX PLL
select
LOCAL
DIVIDER
3.125 Gbps
digital+analog logic
clock
mux
RX CHANNEL 1
3.125 Gbps
RX PLL
3.125 Gbps
digital+analog logic
2–119
Based on what you have set up
as the input clock source for
CMU1 PLL, this clock mux
selects the corresponding input
clock source for CMU1 PLL.
full duplex transceiver channel 2
TX CHANNEL 2
Logical
TX PLL
select
LOCAL
DIVIDER
1 Gbps
digital+analog logic
RX CHANNEL 2
clock
mux
1 Gbps
RX PLL
1 Gbps
digital+analog logic
© June 2009 Altera Corporation
HardCopy IV Device Handbook, Volume 3