HC4GX15 Datasheet, PDF (293/668 Pages) Altera Corporation – HardCopy IV Device Handbook

Chapter 1: HardCopy IV GX Transceiver Architecture
1–29
CMU Channels
Configuring CMU Channels as Transceiver Channels
The two CMU channels in the transceiver block can be configured as a transceiver
channel to run between 600 Mbps and 6.5 Gbps. Figure 1–13 shows the functional
blocks that are enabled to support the transceiver channel functionality.
Figure 1–13. Functional Blocks Enabled to Support Transceiver Channel Functionality
High-speed clock
from the adjacent
CMU channel
x4 clock line
From xN From xN
top
bottom
clock line clock line
From the
core fabric
To the
core fabric
CMU Channel
CMU Clock
divider block
(/1, /2, /4)
tx_data_out
tx_data_in
CMU PLL
CONFIGURED AS
RX CDR
serializer
deserializer
1 The CMU PLL is configured as a CDR to recover data. The dedicated input reference
clock pin is configured to receive serial data.
Table 1–3 shows the pins that are used as transmit and receive serial pins.
Table 1–3. Pins Used as Transmit and Receive Serial Pins (Part 1 of 2)
Pins (1)
REFCLK_[L,R][0,2,4,6]P,
GXB_CMURX_[L_R][0,2,4,6]P
(2)
GXB_TX_[L,R][0,2,4,6] (2)
REFCLK_[L,R][1,3,5,7]P,
GXB_CMURX_[L_R][1,3,5,7]P
(3)
When a CMU Channel is
Configured as a Transceiver
Channel
Receive serial input for CMU
Channel0
When a CMU Channel
is Configured for
Clock Generation
Input reference clocks
Transmit serial output for CMU
Channel0
Receive serial input for CMU
Channel1
Not available for use
Input reference clocks
© June 2009 Altera Corporation
HardCopy IV Device Handbook Volume 3